The LO Raman peaks of annealed (1 0 0) n-InAs wafers disappear with increasing annealing temperature, indicating the elimination of surface electron accumulation layers.
Amorphous In2O3 and As2O3 phases are formed at InAs surface during annealing and a thin crystalline As layer at the interface between the oxidized layer and InAs wafer is also generated.
The thickness of surface electron accumulation layers decreases with increasing annealing temperature since the amount of generated As adatoms acting as acceptor impurities increases.
The influence of annealing temperature on the optical properties of surface electron accumulation layers in n-type (1 0 0) InAs wafers has been investigated by Raman spectroscopy. It exhibits that Raman peaks due to scattering by unscreened LO phonons disappear with increasing temperature, which indicates that the electron accumulation layer in InAs surface is eliminated by annealing. The involved mechanism was analyzed by X-ray photoelectron spectroscopy, X-ray diffraction and high-resolution transmission electron microscopy. The results show that amorphous In2O3 and As2O3 phases are formed at InAs surface during annealing and, meanwhile, a thin crystalline As layer at the interface between the oxidized layer and the wafer is also generated which leads to a decrease in thickness of the surface electron accumulation layer since As adatoms introduce acceptor type surface states.
Surface charge accumulation layer
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Advanced synthesis of semiconductor nanowires (NWs) enables their application in diverse fields, notably in chemical and electrical sensing, photovoltaics, or quantum electronic devices. In particular, indium arsenide (InAs) NWs are an ideal platform for quantum devices, e.g. they may host topological Majorana states. While the synthesis has been continously perfected, only a few techniques have been developed to tailor individual NWs after growth. Here we present three wet chemical etch methods for the post-growth morphological engineering of InAs NWs on the sub-100 nm scale. The first two methods allow the formation of self-aligned electrical contacts to etched NWs, while the third method results in conical shaped NW profiles ideal for creating smooth electrical potential gradients and shallow barriers. Low temperature experiments show that NWs with etched segments have stable transport characteristics and can serve as building blocks of quantum electronic devices. As an example we report the formation of a single electrically stable quantum dot between two etched NW segments.