In this report, we present results of an experimental investigation of a near mid-gap trap energy level in InAs10 ML/GaSb10 ML type-II superlattices. Using thermal analysis of dark current, Fourier transform photoluminescence and low-frequency noise spectroscopy, we have examined several wafers and diodes with similar period design and the same macroscopic construction. All characterization techniques gave nearly the same value of about 140 meV independent of substrate type. Additionally, photoluminescence spectra show that the transition related to the trap centre is temperature independent. The presented methodology for thermal analysis of dark current characteristics should be useful to easily estimate the position of deep energy levels in superlattice photodiodes.
Micro-Raman imaging along with other techniques are applied to study the morphology, structure and crystalline quality of various types of InAs nanowires (NWs). The NWs of low and high densities are formed using metal organic vapor phase epitaxy. Raman mapping is effectively used as a local probe to gain information about the structure and crystalline quality of low-density NWs where the conventional characterization techniques are not very useful. However, for high-density NWs, the image and crystalline quality obtained from the LO phonon strongly corroborate with scanning electron microscopy and x-ray diffraction (XRD) results, respectively. These low-density (104 cm−2) and high-density (108 cm−2) NWs are grown on Si(0 0 1) under various growth conditions such as catalyst-assisted and catalyst-free growth, growth on native oxide-covered and oxide-cleaned Si, grooved Si surfaces and also varying the V/III ratio and growth temperature. NWs (1 µm long and 50–100 nm wide) with high density and tapered NWs (50–80 µm long and 200–500 nm wide at the tip) with low density are formed under different growth conditions. The growth of hillock- and wire-like structures is observed under the same growth condition. Raman, XRD, scanning electron microscopy and atomic force microscopy analyses confirm that the hillocks are grown along the 〈0 0 1〉 direction, whereas the wires are grown along [1 1 0] directions in the plane of Si(0 0 1). Furthermore, the Raman analysis of these NWs confirms that the smaller NWs have much better crystalline quality (half-width of LO phonon frequency ~6 cm−1) compared to the larger NWs (half-width of LO phonon frequency ~15 cm−1) although both NWs are oriented with the Si(0 0 1) surface.
Source:IOPscience
We report a non-lithographical method for the fabrication of ultra-thin silicon (Si) nanowire (NW) and nano-sheet arrays through metal-assisted-chemical-etching (MacEtch) with gold (Au). The mask used for metal patterning is a vertical InAs NW array grown on a Si substrate via catalyst-free, strain-induced, one-dimensional heteroepitaxy. Depending on the Au evaporation angle, the shape and size of the InAs NWs are transferred to Si by Au-MacEtch as is (NWs) or in its projection (nano-sheets). The Si NWs formed have diameters in the range of ~25–95 nm, and aspect ratios as high as 250 in only 5 min etch time. The formation process is entirely free of organic chemicals, ensuring pristine Au–Si interfaces, which is one of the most critical requirements for high yield and reproducible MacEtch.
Source:IOPscience
We report metal–organic vapor-phase epitaxy (MOVPE) growth of pseudomorphic AlAs/InGaAs/InAs resonant tunneling diodes (RTDs) on InP substrates for the first time. X-ray diffraction (XRD) measurements and transmission electron microscopy (TEM) observations reveal that a uniform strained InAs subwell is coherently grown in the double-barrier (DB) structure. The AlAs/InGaAs/InAs RTDs exhibit excellent current–voltage characteristics with a high peak current density (JP) of around 2 × 105 A/cm2 and peak-to-valley ratio (PVR) of around 6. A comparison with control RTDs consisting of AlAs/In0.8Ga0.2As DB confirms the effectiveness of InAs subwell insertion for the improvement of PVR.
Source:IOPscience
This study reports the development of InAs-channel MOSFETs using PECVD-deposited SiO2 gate dielectrics. Arsenic capping and desorption are applied to as-grown wafers to prevent the formation of native oxides before the gate dielectrics are then deposited. We believe that increased hole confinement in a layer structure effectively suppresses the impact ionization effect, and an output conductance as 18 mS/mm at a drain bias of 2 V is demonstrated. A 2 μm-gate-length device exhibits dc performances of IDSS = 154 mA/mm and gm = 189 mS/mm, and rf performances of fT = 14.5 GHz and fMAX = 24 GHz. The InAs-channel MOSFET has potential for application in high frequency circuit devices.
Source:IOPscience
